sta

The next generation of OpenLane, rewritten from scratch with a modular architecture

Codex-first, vendor-neutral RTL coding and verification skill using open-source tools

[ACL 2025] Beyond Prompt Engineering: Robust Behavior Control in LLMs via Steering Target Atoms

Free and extensible software that helps you keep track of you coding statistics

⚙️ A Sensor Things API parser

Parse tokens from an string into an array

Ṛta — deterministic SDC constraint intelligence for block-level VLSI design. Validate, generate, lint, convert and analyze timing constraints before STA, with clock intelligence, coverage, conflict detection, readiness scoring, diff, MMC and CI gates. 1,200+ tests, 119 rules, fully offline — no LLM.

Subtomogram averaging tools for OME-Zarr tilt series.

Dependency-free static timing analysis (STA) engine in pure Python: parses Liberty, gate-level Verilog and SDC, computes setup/hold slack and visualises timing waveforms.

Tech Stack: Python, JavaScript, MLflow, Scikit-Learn, DeepEval, MCML, FPDF2, Pandas, Matplotlib, Fairlearn, spaCy, etc

GY_61 3 axis acceleromter module example using rpi pico for aircraft roll stabilization

A static timing analyzer for digital circuits, built from first principles in Python: Liberty/NLDM delay model, gate-level Verilog + SDC parsing, timing graph, and WNS/TNS + critical-path reporting.

Lightweight mock EDA signoff flow: parse STA timing reports, summarize violations, and visualize slack distribution.

Parser and interactive visualizer for Liberty (.lib) STA timing files — verified across Sky130, NanGate45, GF180MCU, and IHP SG13G2